This invention relates to an intermediate potential generation circuit for generating an intermediate potential between power source voltages, and in particular, the intermediate potential generation circuit which is formed in a semiconductor integrated circuit and which generates a power supply having the intermediate potential from an applied power supply voltage.
For instance, disclosure has been made about an intermediate potential generation circuit in Japanese Unexamined Patent Publication No. Sho. 63-12010 (namely, 12010/1988, thereinafter, referred to as a conventional reference). In such an intermediate potential generation circuit, it is required as a basic function to generate a constant voltage irrespective of a large current.
Specifically, the above-mentioned intermediate potential generation circuit is generally composed of an intermediate potential generation portion and an output portion.
Specifically, a first resistor, an N-channel MOS transistor, a P-channel MOS transistor and a second resistor are serially connected in this order between power sources VDD and VSS in the above intermediate potential generation portion. On the other hand, both an N-channel MOS transistor and a P-channel MOS transistor are connected in series between the power sources VDD and VSS in the output portion.
As mentioned before, the first and second resistors are serially connected to the MOS transistor. In consequence, a response time for potential variation largely depends upon a load device, such as the resistors, in which the resistance value is invariable. Therefore, it is necessary to reduce the resistance value of the resistor in order to improve resistance to a noise and reduce an affect due to the noise.
However, consumption current inevitably becomes large in this case. Thus, there is a trade-off relationship between improvement of resistance to the noise and a low consumption current in the above conventional intermediate potential generation circuit.
Further, it is necessary to connect a plurality of MOS transistors having a low resistance in series in a gate array. This is because it is difficult to arrange a load device having a high resistance in the above gate array.
Consequently, the layout area is inevitably increased to arrange a plurality of MOS transistors in the semiconductor integrated circuit.